The present invention relates to a semiconductor memory and, more particularly, to a circuit technology suitable to attain a high speed memory having memory cells constructed by including field effect transistors (FET).
In recent years, to attain both high density and high speed for a memory, a number of circuits have been proposed using both field effect transistors and bipolar transistors. As an example of such circuits, there has been known a circuit disclosed in the paper entitled, "An 8 ns BiCMOS 1 Mb ECL SRAM with a Configurable Memory Array Size", ISSCC Digest of Technical Papers, pp. 36-37, 1989. According to the above circuit, the memory cell is constructed by a metal-insulator-silicon (MIS) field effect transistor suitable to attain a high density, a differential amplifier to detect a voltage of a bit line is constructed by a bipolar transistor whose base is connected to the bit line, and a circuit to supply a charge current to the bit line is constructed by a bipolar transistor whose emitter is connected to the bit line through a resistor. That is, the area of the memory cell is reduced by the MIS FET suitable to attain a high density and the sensing time of the bit line voltage and the charge time of the bit line are reduced by the bipolar transistor suitable to attain a high speed. However, since the circuit to activate the differential amplifier to detect the voltage of the bit line and the circuit to supply the discharge current to the bit line are constructed by the MIS field effect transistors, there is a limitation to reduce the switching time which is required to activate the differential amplifier and the discharge time of the bit line.